1. Technical Field of the Invention
This invention relates generally to digital circuitry and more in particular to differential digital circuitry.
2. Description of Related Art
Digital logic circuits, such as AND gates, NAND gates, NOR gates, OR gates, exclusive OR gates, latches, inverters, flip-flops, et cetera, are known to be used in a wide variety of electronic devices. For instance, digital logic circuits are used in all types of computers (e.g., laptops, personal computers, personal digital assistants, Internet, infrastructure equipment, telecommunication infrastructure equipment, et cetera), entertainment equipment (e.g., receivers, televisions, et cetera), and wireless communication devices (e.g., cellular telephones, radios, wireless local area networks, et cetera).
Typically, digital logic circuits are part of a larger circuit, which is fabricated as an integrated circuit. For example, a local oscillator within a radio frequency transmitter and/or receiver includes a plurality of flip-flops in its divider feedback section to provide adjustable divider values. As is known, by adjusting the divider value in a local oscillator, the resulting local oscillation can be adjusted to desired values.
As is also known, high performance applications, such as a radio frequency transmitter/receiver integrated circuit (IC), use differential signaling throughout the signal path to improve noise immunity. Accordingly, the circuits processing the differential signaling are differential circuits. For digital differential circuits, including digital logic circuits, a differential clock is needed to produce a 2-phase clock signal. Ideally, the two phases of the clock are complimentary (i.e., the inverse of each other) such that digital differential circuits produce complimentary output data. In practice, however, an ideal differential clock that has perfect complimentary phases is impossible to achieve due to component mismatches, IC process variations, et cetera, which result in rise and fall time mismatches of the 2phases.
In lower rate applications, these mismatches are negligible and digital differential circuits clocked thereby operate sufficiently well. However, as the operating rates increase to the limits of integrated circuit fabrication processes (e.g., CMOS, gallium arsenide, silicon germanium), the mismatches are no longer negligible and, as such, digital differential circuits produce non-complimentary differential outputs, which leads to erroneous output values. Such errors are exasperated when the digital differential circuits are cascaded together, when the differential clock is passed through several inverter stages, or when the differential clock drives large loads.
Therefore, a need exists for a digital differential circuit for use in a high performance application, such as a radio frequency integrated circuit, that is insensitive to non-complimentary differential clocks and produces accurate complimentary digital outputs.
The differential latch and applications thereof substantially meet these needs and others. In one embodiment of a differential latch, it includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal.
The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 1st and 2nd clocking logic operations insure that the sample transistor section is coupled to VDD and VSS at substantially the same time regardless of skewing of the differential clock signal (i.e., the clock phases being non-complimentary). The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation. The 3rd and 4th clocking logic operations ensure that the hold transistor section is coupled to VDD and VSS at substantially the same time regardless of clock skewing. As such, by utilizing the 1st and 2nd gating circuits to trigger the sampling and holding of a differential latch, an accurate differential latch is achieved even though it is being triggered by a non-complimentary differential clock.
A flip-flop may be achieved by using a pair of differential latches coupled in series. Each of the differential latches includes the sample transistor section, the hold transistor section, the 1st gating circuit and the 2nd gating circuit. A plurality of such flip-flops may be used in a divider section of a local oscillator to provide various divider values. Further, such a local oscillator, or oscillation synthesizer, may be used in a radio frequency integrated circuit. By utilizing such a differential latch in a flip-flop, local oscillator and/or radio frequency integrated circuit, the performance of such devices is improved since the differential latch is insensitive to non-complimentary phases of a differential clock.